Need to put the common QSPI parameters in the socfpga.dtsi instead of repeating them for each deviceĬustomer having problems using both hps ethernetsĬould not use both EMAC0 and EMAC1 at the same time C8ES is actually C7 part that is capable to run that speed. I happens only on specific setup.ĬV SoC GHRD has Critical Warnings - timing not metĬV SoC GHRD compiles 400MHz EMIF 800MHz MPU for C8ES device. MAC counter overflow interrupt condition is not treated correctly. Requires a hard reset for a USB host to be able to detect the USB device againĪ board at Wind River may be triggering our MAC counters USB device driver for SoCFPGA does not transition to a correct state when unplugged from a host. Will be fixed by switching to dwc2 USB driver USB Host Detection does not work reliably. USB Host Mode does not work with DMA mode. They will be documented in linux/Documentation/devicetree/bindings SPI Driver Device Bindings are not documented. Using any other PHY device is not possibleĭocument the designware SPI driver bindings under Documentation/devicetree Linux emac driver currently supports only the micrel 9021Ĭurrent Linux EMAC driver supports only one Micrel 9021 PHY device. The function stmmac_tx_timeout needs to be updated to properly follow the datasheet recommendations Stmmac_tx_timeout() is very broken the linux ethernet driver Jumbo ethernet support in HPS/STMMAC controller driver?Įthernet jumbo frames (MTU>1500) are not properly supported In the future they need to be in the Device Tree PHY settings are hardcoded in the driver, making them harder to edit. Transmit offloading on receive side doesn't produce a speed improvementĮthernet checksum calculation is not correctly offloaded from CPU to hardwareĮthernet Phy settings are hard coded in the driver Running instead of 100KHz because onboard LCD does not support 100KHz U-boot, Linux kernel and Yocto source packages are also provided through the git trees at, as shown in the table below. The Cyclone V and Arria V precompiled binaries archives ( and ) contain the following files: The following documents are also part of the release: The GSRD sources and prebuilt binaries can be downloaded from. To let the kernel trace functions, you need to turn on ftrace, by running:Įcho 1 > /sys/kernel/debug/tracking/tracing_on For more information about ftrace, please start with the introduction on the Linux Weekly Newsletter web site. New drivers: FPGA bridges, DMA, QSPI, Watchdog.Drivers: I2C, LCD, EEPROM, RTC, Ethernet, USB (Host), Watchdog, SD/MMC, QSPI, DMA, FPGA Manager, and FPGA Bridges.This Linux BSP release supports the CycloneV SoC Development Kit, and provides the following for the CycloneV SoC: Always use the GHRD that is delivered as part of GSRD. Note: Do not use the GHRD that is part of SoC EDS with the GSRD. Both DTG and DTC are released as part of SoCEDS. Device tree is generated with DTG and compiled using DTC.Content for the target web server has been removed from Yocto repository and is now bundled in the GSRD source tar ball.U-boot is enabled to use a script for boot customization.U-boot is built in Yocto instead of SoCEDS. U-boot code base no longer relies on handoff information.FPGA image is programmed from U-boot instead of via CFI flash through PFL mega function.Preloader has been configured with watchdog enabled.CV SoCFPGA GHRD is upgraded to support rev D board with C6 part and new QSPI flash component.GSRD packages are no longer be released with kit installer at Altera portal.AV SoCFPGA GSRD has been created, and it has the same set of software features as CV SoCFPGA GSRD.CV SoCFPGA GSRD has been updated to ACDS13.1 code base using ACDS13.1 tools and software release.Terasic Stratix 10 SoC Board : DE10-Pro.Terasic Stratix 10 SoC Board : Apollo S10 SoM.REFLEX CES COMXpressSX Stratix 10 Module.Terasic DE1-SoC Development and Education Board.Solectrix SMARC compliant System-on-Module.Networked Pro-Audio FPGA SoC Development Kit by Coveloz.Mpression Borax SOM Module and Development Kit by Macnica.Mpression Sodia Evaluation Board by Macnica.Mpression Helio SoC Evaluation Kit by Macnica.Altera Cyclone V SoC Development Platform.Critical Link MitySOM-5CSx Development Kit.Arrow SoCKit User Manual - November 2019 Edition.Arrow SoCKit User Manual - July 2017 Edition.Terasic Arria10 SoC Board : HAN Pilot Platform.Nallatech 510T compute acceleration card with Intel Arria 10 FPGA.ALARIC Instant DevKit ARRIA 10 SoC FMC IDK by REFLEX CES.Nallatech 385A-SoC Accelerator Card with Arria 10 FPGA.Nallatech 385A - Arria 10 FPGA Network Accelerator Card.
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